On 2025-05-29 at 23:40, Sean Christopherson wrote:
> @@ -81,70 +79,6 @@ static uint64_t osvw_len = 4, osvw_status;
>
> static DEFINE_PER_CPU(u64, current_tsc_ratio);
>
> -static const u32 direct_access_msrs[] = {
> - MSR_STAR,
> - MSR_IA32_SYSENTER_CS,
> - MSR_IA32_SYSENTER_EIP,
> - MSR_IA32_SYSENTER_ESP,
> -#ifdef CONFIG_X86_64
> - MSR_GS_BASE,
> - MSR_FS_BASE,
> - MSR_KERNEL_GS_BASE,
> - MSR_LSTAR,
> - MSR_CSTAR,
> - MSR_SYSCALL_MASK,
> -#endif
> - MSR_IA32_SPEC_CTRL,
> - MSR_IA32_PRED_CMD,
> - MSR_IA32_FLUSH_CMD,
> - MSR_IA32_DEBUGCTLMSR,
> - MSR_IA32_LASTBRANCHFROMIP,
> - MSR_IA32_LASTBRANCHTOIP,
> - MSR_IA32_LASTINTFROMIP,
> - MSR_IA32_LASTINTTOIP,
> - MSR_IA32_XSS,
> - MSR_EFER,
> - MSR_IA32_CR_PAT,
> - MSR_AMD64_SEV_ES_GHCB,
> - MSR_TSC_AUX,
> - X2APIC_MSR(APIC_ID),
> - X2APIC_MSR(APIC_LVR),
> - X2APIC_MSR(APIC_TASKPRI),
> - X2APIC_MSR(APIC_ARBPRI),
> - X2APIC_MSR(APIC_PROCPRI),
> - X2APIC_MSR(APIC_EOI),
> - X2APIC_MSR(APIC_RRR),
> - X2APIC_MSR(APIC_LDR),
> - X2APIC_MSR(APIC_DFR),
> - X2APIC_MSR(APIC_SPIV),
> - X2APIC_MSR(APIC_ISR),
> - X2APIC_MSR(APIC_TMR),
> - X2APIC_MSR(APIC_IRR),
> - X2APIC_MSR(APIC_ESR),
> - X2APIC_MSR(APIC_ICR),
> - X2APIC_MSR(APIC_ICR2),
> -
> - /*
> - * Note:
> - * AMD does not virtualize APIC TSC-deadline timer mode, but it
> is
> - * emulated by KVM. When setting APIC LVTT (0x832) register bit
> 18,
> - * the AVIC hardware would generate GP fault. Therefore, always
> - * intercept the MSR 0x832, and do not setup direct_access_msr.
> - */
> - X2APIC_MSR(APIC_LVTTHMR),
> - X2APIC_MSR(APIC_LVTPC),
> - X2APIC_MSR(APIC_LVT0),
> - X2APIC_MSR(APIC_LVT1),
> - X2APIC_MSR(APIC_LVTERR),
> - X2APIC_MSR(APIC_TMICT),
> - X2APIC_MSR(APIC_TMCCT),
> - X2APIC_MSR(APIC_TDCR),
> -};
> -
> -static_assert(ARRAY_SIZE(direct_access_msrs) ==
> - MAX_DIRECT_ACCESS_MSRS - 6 * !IS_ENABLED(CONFIG_X86_64));
> -#undef MAX_DIRECT_ACCESS_MSRS
The MAX_DIRECT_ACCESS_MSRS define should now be removed from
arch/x86/kvm/svm/svm.harch/x86/kvm/svm/svm.h, since it's no longer used.
