Explicitly zero PERF_GLOBAL_CTRL at the start of the PMU test as the
architectural RESET value of PERF_GLOBAL_CTRL is to set all enable bits
for general purpose counters (for backwards compatibility with software
that was written for v1 PMUs). Leaving PERF_GLOBAL_CTRL set can result in
false failures due to counters unexpectedly being left active.
Signed-off-by: Sean Christopherson <seanjc@xxxxxxxxxx>
---
x86/pmu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/x86/pmu.c b/x86/pmu.c
index 8cf26b12..9bd0c186 100644
--- a/x86/pmu.c
+++ b/x86/pmu.c
@@ -905,9 +905,6 @@ static void set_ref_cycle_expectations(void)
if (!pmu.nr_gp_counters || !pmu_gp_counter_is_available(2))
return;
- if (this_cpu_has_perf_global_ctrl())
- wrmsr(pmu.msr_global_ctl, 0);
-
t0 = fenced_rdtsc();
start_event(&cnt);
t1 = fenced_rdtsc();
@@ -956,6 +953,9 @@ int main(int ac, char **av)
handle_irq(PMI_VECTOR, cnt_overflow);
buf = malloc(N*64);
+ if (this_cpu_has_perf_global_ctrl())
+ wrmsr(pmu.msr_global_ctl, 0);
+
check_invalid_rdpmc_gp();
if (pmu.is_intel) {
base-commit: 72d110d8286baf1b355301cc8c8bdb42be2663fb
--
2.49.0.1204.g71687c7c1d-goog
