On Wed, May 14, 2025 at 12:13 PM Atish Patra <atishp@xxxxxxxxxxxx> wrote: > > The KVM virtualizes PMU in RISC-V and disables all counter access except > TM bit by default vi hstateen CSR. There is no benefit in enabling CY/TM > bits in scounteren for the guest user space as it can't be run without > hcounteren anyways. > > Allow only TM bit which matches the hcounteren default setting. > > Signed-off-by: Atish Patra <atishp@xxxxxxxxxxxx> > --- > arch/riscv/kvm/vcpu.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c > index 60d684c76c58..873593bfe610 100644 > --- a/arch/riscv/kvm/vcpu.c > +++ b/arch/riscv/kvm/vcpu.c > @@ -146,8 +146,8 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) > if (kvm_riscv_vcpu_alloc_vector_context(vcpu, cntx)) > return -ENOMEM; > > - /* By default, make CY, TM, and IR counters accessible in VU mode */ > - reset_csr->scounteren = 0x7; > + /* By default, only TM should be accessible in VU mode */ > + reset_csr->scounteren = 0x2; Let's remove this as well because the Linux SBI PMU driver does initialize scounteren correctly. Regards, Anup
