On 5/5/25 05:44, Huang, Kai wrote:
>> +static int tdx_pamt_add(atomic_t *pamt_refcount, unsigned long hpa,
>> + struct list_head *pamt_pages)
>> +{
>> + u64 err;
>> +
>> + hpa = ALIGN_DOWN(hpa, SZ_2M);
>> +
>> + spin_lock(&pamt_lock);
> Just curious, Can the lock be per-2M-range?
Folks, please keep it simple.
If there's lock contention on this, we'll fix the lock contention, or
hash the physical address into a fixed number of locks. But having it be
per-2M-range sounds awful. Then you have to size it, and allocate it and
then resize it if there's ever hotplug, etc...
Kirill, could you put together some kind of torture test for this,
please? I would imagine a workload which is sitting in a loop setting up
and tearing down VMs on a bunch of CPUs would do it.
That ^ would be the worst possible case, I think. If you don't see lock
contention there, you'll hopefully never see it on real systems.
I *suspect* that real systems will get bottlenecked somewhere in the
page conversion process rather than on this lock. But it should be a
pretty simple experiment to run.
