On Sat, Apr 26, 2025 at 01:28:07PM +0100, Marc Zyngier wrote: > Provide the architected EC and ISS values for all the FEAT_LS64* > instructions. > > Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx> > --- > arch/arm64/include/asm/esr.h | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h > index e4f77757937e6..a0ae66dd65da9 100644 > --- a/arch/arm64/include/asm/esr.h > +++ b/arch/arm64/include/asm/esr.h > @@ -20,7 +20,8 @@ > #define ESR_ELx_EC_FP_ASIMD UL(0x07) > #define ESR_ELx_EC_CP10_ID UL(0x08) /* EL2 only */ > #define ESR_ELx_EC_PAC UL(0x09) /* EL2 and above */ > -/* Unallocated EC: 0x0A - 0x0B */ > +#define ESR_ELx_EC_OTHER UL(0x0A) > +/* Unallocated EC: 0x0B */ > #define ESR_ELx_EC_CP14_64 UL(0x0C) > #define ESR_ELx_EC_BTI UL(0x0D) > #define ESR_ELx_EC_ILL UL(0x0E) > @@ -181,6 +182,11 @@ > #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0) > #define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1) > > +/* ISS definitions for LD64B/ST64B instructions */ > +#define ESR_ELx_ISS_OTHER_ST64BV (0) > +#define ESR_ELx_ISS_OTHER_ST64BV0 (1) > +#define ESR_ELx_ISS_OTHER_LDST64B (2) > + > #define DISR_EL1_IDS (UL(1) << 24) > /* > * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean Reviewed-by: Joey Gouly <joey.gouly@xxxxxxx>
