On Tue, Apr 01, 2025 at 05:22:38PM -0700, Sean Christopherson wrote: > On Wed, Apr 02, 2025, Yan Zhao wrote: > > On Tue, Apr 01, 2025 at 03:11:07PM -0700, Sean Christopherson wrote: > > > Add back support for honoring guest PAT on Intel CPUs that support self- > > > snoop (and don't have errata), but guarded by a quirk so as not to break > > > existing setups that subtly relied on KVM forcing WB for synthetic > > > devices. > > > > > > This effectively reverts commit 9d70f3fec14421e793ffbc0ec2f739b24e534900 > > > and reapplies 377b2f359d1f71c75f8cc352b5c81f2210312d83, but with a quirk. > > > > > > Cc: Yan Zhao <yan.y.zhao@xxxxxxxxx> > > > Signed-off-by: Sean Christopherson <seanjc@xxxxxxxxxx> > > > --- > > > > > Hi Sean, > > > > > AFAIK, we don't have an answer as to whether the slow UC behavior on CLX+ > > > is working as intended or a CPU flaw, which Paolo was hoping we would get > > We did answer the slow UC behavior is working as intended at [1]. > > > > "After consulting with CPU architects, > > it's told that this behavior is expected on ICX/SPR Xeon platforms due to > > the snooping implementation." > > > > Paolo then help update the series to v2 [2] /v3 [3]. > > > > Did you overlook those series, or is there something I missed? > > Nope, you didn't miss anything. I have that series in my TODO folder, but only > glanced at it when it flew by and completely missed that it quirks ignoring > guest PAT. Not sure how I missed the cover letter subject though... > > Anyways, ignore this, my bad. Thanks for the update, and sorry for the noise! That's OK :)
