AW: ARMv7: VLDR instruction for unaligned address (GCC 9.5.0)

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Hello!

I've found the commit that makes the generated code work: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=c7207339a7dbce5b68f872064e624dcf1639ba46.

If I understand the commit message correctly, this change reduces the number of CPU registers in use, thus eliminating the need for the compiler to resort to using FPU registers. If that is true, then it's still possible that we might run into alignment issues again, should the compiler ever be put under enough register pressure. Is that correct?

Christian




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