On Thu, Jun 19, 2025 at 5:55 PM Eduard Zingerman <eddyz87@xxxxxxxxx> wrote:
>
> On Thu, 2025-06-19 at 17:13 -0400, Harishankar Vishwanathan wrote:
> > On Wed, Jun 18, 2025 at 5:22 PM Eduard Zingerman <eddyz87@xxxxxxxxx> wrote:
> > >
> > > On Tue, 2025-06-17 at 19:17 -0400, Harishankar Vishwanathan wrote:
[...]
> Hm, I see, that's an interesting angle.
> The problem is, if I do something silly changing the code and this
> test fails I'd have a hard time understanding the expected output.
> Therefore, I'd prefer something more obvious.
>
> Maybe let's go with this:
>
> SEC("tc")
> __success
> __naked void test1(void)
> {
> asm volatile (
> "r3 = 0xa000000000000000 ll;"
> "r4 = 0x0;"
> "r4 = -r4;"
> "r3 |= r4;"
> "r3 += r3;"
> "r0 = 1;"
> "exit;"
> :
> : __imm(bpf_get_prandom_u32)
> : __clobber_all);
> }
>
> Here is verifier log comparison:
>
> master: 5: (0f) r3 += r3 ; R3_w=scalar()
> branch: 5: (0f) r3 += r3 ; R3_w=scalar(umin=0x4000000000000000,umax=0xfffffffffffffffe)
>
> ?
Okay, this seems both readable and also demonstrates precision gains.
I'll follow up with a
v3 with similar updated test cases for full overflow and partial
overflow for all the four functions.
[...]
