On Thu, Feb 27, 2025 at 10:00 PM Eduard Zingerman <eddyz87@xxxxxxxxx> wrote: > > This patch set introduces a simple live register DFA analysis. > The analysis is performed as a separate step before the main > verification pass, and results are stored in `env->insn_aux_data` for > each instruction. > > This change improves handling of iterator/callback-based loops, as > regular register liveness marks are not finalized while loops are > being processed. See veristat results for selftests and sched_ext in > patch #2. > > The patch set was tested in branch [1] by disabling the current > register parentage chain liveness computation, using DFA-based > liveness for registers while assuming all stack slots as live. > No notable regressions were found in test_progs-based tests. I think the end goal is to get rid of mark_reg_read() and switch to proper live reg analysis. So please include the numbers to see how much work left. Also note that mark_reg_read() tracks 32 vs 64 reads separately. iirc we did it to support fine grain mark_insn_zext to help architectures where zext has to be inserted by JIT. I'm not sure whether new liveness has to do it as well.
